Signal and Power Integrity Co-Analysis of Chiplet(UCIe)-based GPU-HBM Interconnect for Reduced PHY Area

This paper proposes an SI/PI co-analysis framework for the GPU–HBM interconnect, comparing a conventional wide I/O-based configuration with a chiplet (UCIe)-based configuration under an iso-bandwidth condition. First, routability-aware interposer channels are designed based on shoreline pitch limitations, and 3D electromagnetic simulation is performed to extract loss and crosstalk including microbump effects. Second, a hierarchical PDN model is constructed to obtain PDN impedance and simultaneous switching noise (SSN). The SI and PI results are then integrated through power-supply-induced jitter (PSIJ), which is computed by combining SSN with driver-derived jitter sensitivity and channel-dependent jitter amplification. The result show that the chiplet-based configuration achieves a peak-to-peak PSIJ of 0.56 ps (0.018 UI), compared with 3.44 ps (0.028 UI) for the conventional wide I/O-based configuration, while reducing the PHY area by 80%. Hence, the chiplet-based GPU–HBM can both improve area efficiency and SI/PI robustness, making them a promising solution for next-generation AI hardware.