Scalable UVM Verification Components (UVCs) to Accelerate Functional Verification of SoCs

The functional verification is an important step in system on chip (SoC) design process. Generally, the SoC consists of a processor with peripherals, interconnects, on-chip memories with error correction code (ECC) based schemes and communication protocols. An error-free SoC requires the individual blocks to be verified at IP, subsystem and SoC level. Therefore, there is need of such verification techniques and platform which are completely reusable at all levels of verification. The universal verification methodology (UVM) is an industry standard and is widely used for verifying functionality of SoCs nowadays. It is worth mentioning that the existing open source UVCs can only be easily used for IP level verification and a lot of human effort is required to tailor them for subsystem and SoC-level verification frameworks. In this paper, scalable UVM Verification Components (UVCs) are proposed that are robust enough to be used at IP, subsystem and SoC level. The proposed UVCs are: 1) Fault-injection for ECC based memories, 2) APB, 3) Wishbone, 4) SPI, 5) UART, 6), GPIO and 7) Clk-Reset. Moreover, a purposely designed fault injecting UVC for ECC based memories ensures that the memory used in RISC-V based SoCs can effectively handle different fault types. The result shows that the UVCs accelerated the functional verification of a RISC-V based SoC and 100% functional coverage closure goals are achieved.