PINS: Power Integrity-Aware Power Delivery Network Synthesis in Interposer-Based Advanced Packaging

In advanced packaging, power delivery network (PDN) design for silicon interposers is increasingly constrained by limited routing resources, preplaced components, and non-uniform current demand across multiple power domains. This paper presents PINS, a power integrity-aware PDN synthesis framework that jointly allocates interposer metal and via resources according to current demand while explicitly accounting for layout obstacles. Unlike geometry-driven methods, PINS embeds physically grounded power integrity metrics directly into the synthesis loop. Experimental results demonstrate substantial reductions in chiplet IR drop and interposer power loss, along with 4× speedup compared to the state-of-the-art approach.