Novel Coupled Via (CV) Feature for Far-end Crosstalk Reduction

The far-end crosstalk (FEXT) from socket pins and motherboard Plated-through-hole (PTH) vias is a major signal integrity performance limiter, especially for crosstalk sensitive single-ended memory signals. A novel passive crosstalk reduction feature called coupled via is proposed to effectively mitigate the risk. This paper demonstrates an on-package implementation of the coupled via concept within existing substrate design rule and cost boundary conditions. The benefits of coupled via was verified through modeling and validation data and it has been adopted for multiple generations of Intel’s CPU products.