Multi-lane SerDes Power Delivery Network Challenges and Decap Optimization

As we move into the complex design of high-speed IOs working at increased datarates of more than 100G, power delivery network (PDN) optimization becomes more challenging. To meet the stringent Power Delivery Network noise specifications, we make sure that the impedance seen by the device meets the target impedance, by optimizing the decap (decoupling capacitor) requirements at PCB, package, and die. Package level decap optimization is one of the major challenges to be addressed to meet the voltage ripple requirements with minimal BOM(Bill of Materials) cost. Here we propose a method to perform the decap optimization of the Serdes with a shared power delivery network, considering the impact of power supply noise coupling in multi-lane shared SerDes. This paper analyses the impact on ripple voltage from different voltage noise sources and explains how the PDN design accuracy can be improved in the frequency domain without having to run the transient simulation every time, which is a time-consuming process and poses challenges to Time-to-Market (TTM) concerns.