Multi-chips High-density Interconnection Design on InFO Platform

With the increase in the difficulty of process breakthroughs, advanced packaging has become a breakthrough for Moore's law to continue. 2.5D advanced packaging technologies can package together processors, memory and other IPs under different processes, which not only avoids the increase in die size, but also With the decline of the yield rate, IP can be selected according to the function, which reduces the development cost and speeds up the product launch. Compared with the silicon interposer board, the InFO package has a greatly reduced cost, and compared to the 2D package, it can achieve multi-chip packging while having good electrical performance. The package design is that one main ASIC chip is connected with two auxiliary ASIC chips, and the two auxiliary ASIC chips are connected. The auxiliary ASIC chip is used to enhance the function of the main ASIC chip. The high-density interconnection adopts the signal layer 2um/2um and the power layer 5um/5um 5-layer RDL wiring method, the frequency is 2.4Ghz, and the data rate is 4.8Gbps. The wiring method adopts the ground isolation reference wiring to ensure high-speed signal integrity. At the same time comparing a variety of wiring structure, the electrical performance under this wiring method is the most superior.