Landside capacitor efficacy among multi-chip-module using Si-interposer

Power delivery network (PDN) impedance reduction is strongly required for recent high-performance graphical-processing-unit, and mo-bileelectronicsthatrequiresmassivedatatransferamonglogicandmemorydice.ToimprovePDNcharacteristics,lowequivalentseriesinductanceandresistance(ESLandESR)arerequiredforcapacitor,aswellaspowerlineroutingincludingplacementofthecapacitor.Inthispaper,wefocusonSi-interposerasamethodtoenableultra-highbitrateaswellasfan-outwaferlevelpackaging.ASi-interposerwithtransmissionlinesismanu-factured,andCMOStestvehicleandlowESLSi-capacitorsaremountedontheSi-interposertoevaluatechip-to-chipcommunicationperformanceonmulti-chip-module(MCM),throughevaluatingpowerlinenoise.Ex-perimentalresultsofin-placewaveformwithphysicallydifferentcapacitortypesandplacementsonSi-interposer,byon-chipwaveformmonitoring(OCM)technology.PDNanalysisclarifiedtheefficacyoflowprofileSi-capacitorsandplacementstrategytominimizeseriesparasiticcomponents,capturedwaveformshowsstabilizeddrainpowervoltage(VDD)waveshapethrough12-channelslow-voltagedifferentialsignaling(LVDS)transceiversoperation.