Key Considerations and Challenges in Post-Layout Simulation for High-Speed Interfaces on PCB Design

As high-speed input/output (I/O) interfaces continue to evolve, the printed-circuit board (PCB) design has become increasingly challenging and complex—particularly in server and AI system applications. Designers must now address the issues for signal integrity in the whole system, to ensure reliable high-speed performance. From the currently prevalent PCI-Express (PCIe) 5.0 standard operating at 32 GT/s, to the forthcoming PCIe 6.0 and the future PCIe 7.0—targeting data rates of 64 GT/s and 128 GT/s respectively [1] —each generation presents significant advancements in bandwidth and corresponding challenges in high-speed PCB design. Moreover, after introducing MRDIMM (Multiplexed Rank Dual In-line Memory Module, also known as MCRDIMM), the speed of the DDR memory interface jumped from 8800 MT/s in Gen.1 to 12,800 MT/s in Gen.2, which is almost reaching the PCIe 4.0 speed but operates in single-ended, not differential mode. From the perspective of system designers, performing accurate signal integrity (SI) simulations is essential in early stages to anticipate real-world behavior and mitigate potential risks prior to product fabrication.