Interconnect-Memory Challenges for Multi-chip, Silicon Interposer Systems
Interconnect-Memory Challenges for Multi-chip, Silicon Interposer Systems
G. Loh,Natalie D. Enright Jerger,Ajaykumar Kannan,Yasuko Eckert
2015 · DOI: 10.1145/2818950.2818951
International Symposium on Memory Systems · 53 Citations
TLDR
Key issues in providing the interconnect support for aggressive interposer-based memory integration are described, and it is argued for additional research efforts to address these challenges to enable integrated memory to deliver its full value.