High-Performance RISC-V Emulation
High-Performance RISC-V Emulation
Leandro Lupori,V. M. Rosário,E. Borin
2018 · DOI: 10.1007/978-3-030-41050-6_9
Symposium on High Performance Computing Systems · 0 Citations
TLDR
This work implemented and evaluated a LLVM-based Static Binary Translation (SBT) engine to investigate whether or not it is possible to produce high-quality translations from RISC-V to x86 and ARM, and designed an SBT engine that produces translated code that is only 1.2x/1.3x slower than native x86/ARM code.