GNN-Curio: Transistor Sizing by Curiosity-Driven Reinforcement Learning with Graph Neural Networks

In recent years, several methods using deep reinforcement learning (DRL) have been published in the field of analog circuit sizing, and all these methods have outperformed previous methods and even human design. However, these are limited to basic circuits with a minimal number of elements and desired specifications, and may not be effective for the large-scale topologies and specifications required in actual design situations. We introduce the Graph Neural Network (GNN)-Curio method, which combines effective feature extraction via GNN with an internal reward scheme named "curiosity" to enable exploration in large-scale topologies and specifications. The GNN-Curio has demonstrated the ability to achieve a Figure of Merit (FoM) with more than tenfold precision for topologies with over 25 elements, which is unattainable by existing DRL methods.