Fabrication and Experimental Characterization of Embedded Multi-Terminal Capacitors With Ultra-Low Parasitics for Integrated Vertical Power Delivery

This paper presents embedded multi-terminal silicon deep-trench capacitors (DTCs) integrated into a glass substrate for vertical power delivery applications, together with experimental characterization for accurate extraction of equivalent series inductance (ESL) and equivalent series resistance (ESR). A 210-μm-thick DTC is embedded within a 300-μm glass substrate using dual 6-μm-thick copper planes separated by a 15-μm polymer dielectric layer, along with an additional 30-μm polymer layer between the glass substrate and the lower copper plane. Two stacked micro-via layers formed within the dielectric stack and interconnected through copper planes provide a total vertical interconnection height of 57μm from the capacitor pads to the top redistribution layer, enabling direct vertical current paths. The proposed embedded structure achieves an equivalent parasitic inductance of ESL <0.5pH and ESR <5mΩ for a 2.8-μF capacitor die under vertical current flow after integration. The extracted parasitic parameters are validated using both single-port and two-port shunt vector network analyzer (VNA) measurements based on S-parameter (S1P and S2P) impedance characterization, highlighting the necessity of two-port shunt measurements for accurate characterization of ultra-low-impedance DTCs.