Efficient Transactional Memory Runtimes for Unmanaged Environments

The adoption of multi-core processors requires programmers to use concurrent programming to fully benefit from the available processing power. Efficient concurrent programming using locks is notoriously difficult to master. This makes the case for alternative concurrent programming paradigms. One of the most promising of these paradigms is Transactional Memory, which uses optimistic execution of code via the concept of transactions. In this thesis, we propose to improve the support and performance of transactional memory for unmanaged environment, at all levels of the system software and hardware stack. First, we improve the performance of software transactional memory by developing LSA, an algorithm based on a virtual clock to ensure transaction consistency. In this context, we propose several optimizations for efficiency and develop features that will favor the uptake and usability of transactional memory for application developers. Next, we extend our Transactional Memory library to leverage the availability of hardware mechanisms that can support the execution of transactions. We show that Hardware Transactional Memory can deliver a high performance compared to software-only approaches but suffers from several limitations. Our Hybrid Transactional Memory, extending on our LSA algorithm, combines the advantages of hardware and software transactional memory to achieve a performance close to pure hardware transactional memory while overcoming its limitations. Finally, we describe the integration of transactional memory in a complete system stack. We describe the standardization of the C/C++ language transactional constructs and the binary interface for transactional memory runtimes. We extend our Transactional Memory library to follow these specifications and make it compliant with two transactional compilers, including GCC. The resulting framework provides developers with an easy and efficient way to create applications that can take advantage of multi-core processors.