Colay Optimization Design and Experimental Verification for High-Speed Signal Multiplexing

With the rapid development of information technology, the demand for computer configurations among industry customers has become increasingly diverse. Therefore, in designing the PCB of a computer motherboard, the adoption of Colay (Compatible-Layout) technology is necessary to achieve signal multiplexing, enabling more complex functions within limited device layout space. However, as chip manufacturing processes are upgraded and data rates increase, the signal integrity issues associated with the traditional Colay topology have become increasingly prominent, posing new challenges for the development of computer boards. In response, this paper focuses on the SATA high-speed signal transmission topology on a PC motherboard and proposes a high-order capacitor-resistor element Colay (HO-Colay) optimization design method. This method effectively addresses the issues of increased jitter and loss in high-speed signal links, which are caused by the traditional Colay topology. Experimental results show that, while reducing the number of devices used and optimizing the layout space, the HO-Colay scheme designed by the authors improves the eye height of the SATA signal by 7%, reduces jitter by 18.9%, significantly reduces signal loss, and improves the impedance continuity of the high-speed signal link, achieving good signal integrity optimization effects.