BGA Routing Impact on High-Speed Signals

To meet the growing demand for data consumption, IO speeds, IO ports, CPU core count and pin density continue to increase every generation. In the last few generations, the number of ports of peripheral component interconnect express (PCIe) and double data rate (DDR) interfaces have nearly doubled in CPUs. Ball grid array (BGA) breakout in current CPUs is becoming a challenge due to the increased density. Significant noise can get coupled to high-speed signals if the package or BGA breakout is less than optimal. In this paper, various BGA breakout schemes that are popularly used are discussed. The advantages and limitations of these schemes are discussed with frequency domain data. In addition, the paper also highlights that trace-to-via fringe coupling at high frequencies can impact high-speed signals adversely