An improved algorithm for deep learning YOLO network based on Xilinx ZYNQ FPGA

With the development of artificial intelligence, convolutional neural networks (CNN) have been widely used in image processing and other aspects due to their excellent performance. However, as a computationally intensive algorithm, CNN face huge challenges in the realization of mobile devices. FPGA have the advantages of high performance, reprogramming, and low power consumption, and have becoming suitable choices for CNN deployment. Compared with various CNN algorithms, the YOLO algorithm regards target detection as a regression problem. It is a one-step algorithm with fast execution speed and small amount of calculation. It is suitable for implementation on FPGA hardware platforms. This paper proposes an improved algorithm for deep learning YOLO network based on Xilinx ZYNQ FPGA. By optimizing the YOLO network model and fixed-point, etc., the problem of large computational of CNN and limited resources on FPGA chips is solved, and the parallelism of FPGA is used to accelerate the CNN. Experimental results show that the method proposed in this paper has greatly improved the operation rate while maintaining accuracy, and has important practical value in the realization of mobile terminals of CNN and real-time computing.