An Automated Circuit Topology Generation and Optimization Method for CMOS Low-Noise Amplifiers

This article presents an automated circuit topology generation and optimization method for RF low-noise amplifiers (LNAs). For circuit topology generation, a three-port small-signal model based on precomputed lookup tables (LUT) is proposed to accurately describe the transistors. Based on the model, a novel predefined building block (PBB) library for LNA is created and symbolically analyzed by three-port network parameters and noise correlation matrix. Then, graph-grammar-based tree structure generation (GTSG) is applied to efficiently realize circuit topology generation. For circuit optimization, the rule-guided non-dominated sorting genetic algorithm (RG-NSGA-II) is applied to optimize the performances of generated circuit topologies. To validate, four typical examples of X-band LNA based on a 130-nm CMOS process are presented, and the results are verified using Spectre. This method can automatically generate 936 size-free circuit topologies, even a variety of inspiring topologies. Compared to traditional NSGA-II, the RG-NSGA-II shows enhanced optimization speed in four examples, with the mean absolute percentage error (MAPE) <5% to Spectre.