An Architecture-Level Framework for Enabling Processing-Using-Memory Simulations in Deep Neural Networks

The emulation or layout in the study of processing-in-memory (PIM) is a highly time-consuming process. Especially, the processing-using-memory (PUM), a subset of PIM, is much more complex due to the positioning of the processing unit in the high-density data array. Because of this reason, it is important to efficiently verify PIM hardware using simulation to activate the PIM study. To this end, we modify the DRAMsim3, a memory simulator, to implement a PUM system, and propose a PIM operation compiler in the Zsim, a CPU simulator. The PIM operation compiler performs the role of tracing instructions from various precision deep neural network (DNN) workloads and generating PIM operation commands. Finally, we propose an architecture-level PUM simulation framework that can simulate the PUM system with DNN workloads based on the PIM command generated by the compiler.