Accelerating Memory Recorder Waveform Analysis via Distributed and General Purpose Accelerator

This article identifies critical inefficiencies in traditional waveform analysis architectures for memory recorders, where function-specific (FS) accelerators and centralized processing on field-programmable gate array (FPGA) incur severe development and service efficiency bottlenecks. FS accelerators for various waveform analysis kernels not only demand labor-intensive manual design but also suffer from exponential FPGA compilation delays and decreased performance due to fine-grained resource contention. Besides, centralized architectures further exacerbate service latency through PXIe bandwidth contention during massive data transfers. To resolve these limitations, this article proposes a general-purpose (GP) accelerator architecture that enables the acceleration of arbitrary builtin and user-defined (UD) waveform analysis kernels via three innovations: 1) a coarse-grained tile array that precombines fine-grained FPGA resources into programmable compute units with dynamic dataflow; 2) a heuristic compiler automating kernel-to-tile mapping through modulo routing resource graphs, eliminating manual design efforts; and 3) distributed deployment across acquisition board FPGAs, localizing computation to eliminate centralized data transfers. Implemented in a self-designed 14-acquisition-board memory recorder prototype, the GP accelerator demonstrates $920 \sim 6670 \times$ of development efficiency enhancement and $8.5 \sim 27.5 \times$ service efficiency improvement over centralized FS accelerators under multikernel scenarios.