A proposed framework for measuring , identifying , and eliminating clock and data jitter on high-speed serial communication links
A proposed framework for measuring , identifying , and eliminating clock and data jitter on high-speed serial communication links
Hamed Sanogo
2010
1 Citations
TLDR
A simple and practical procedure for characterizing high-speed serial data links at 1Gbps and beyond and assumes that the clock and data recovery block of the PHY (physical layer) or SerDes (serializer-deserializer) device complies with the standards applicable to that device.