A passive equalizer and its design methodology for global interconnects in VLSIs
A passive equalizer and its design methodology for global interconnects in VLSIs
M. Yasunaga,Naoki Yokoshima,I. Yoshihara
2016 · DOI: 10.1109/VLSI-SoC.2016.7753552
IEEE/IFIP International Conference on Very Large Scale Integration of System-on-Chip · 0 Citations