A level shifter circuit design by using input/output voltage monitoring technique for ultra-low voltage digital CMOS LSIs
A level shifter circuit design by using input/output voltage monitoring technique for ultra-low voltage digital CMOS LSIs
Yuji Osaki,T. Hirose,N. Kuroki,M. Numa
2011 · DOI: 10.1109/NEWCAS.2011.5981290
IEEE International New Circuits and Systems Conference · 10 Citations