A Cross-Layer Survey on Lattice-Based Post-Quantum Cryptography: Side-Channel Security, Hardware Design, and Secure IoT Protocol Integration

Lattice-based cryptography has emerged as the leading candidate for post-quantum public-key primitives due to strong worst-case hardness guarantees and efficient algebraic structure. As standardization efforts mature, practical deployment increasingly depends on implementation security, hardware feasibility, and protocol-level robustness rather than theoretical security alone. This survey presents a cross-layer analysis integrating recent experimental and analytical results across these dimensions. At the implementation level, we review non-profiled correlation power and electromagnetic attacks targeting polynomial multiplication and NTT-based arithmetic. At the hardware layer, we analyze building-block cost models and ASIC/FPGA trade-offs for NTT, Toom–Cook, and schoolbook multipliers, highlighting performance, memory, and leakage implications. At the protocol layer, we examine reconciliation-enabled RLWE authenticated key exchange schemes for constrained IoT devices and their associated attack surfaces. By consolidating attack vectors, implementation trade-offs, and cross-layer interactions, this survey provides practical guidance for designing secure, efficient, and deployable lattice-based post-quantum systems.