A Comprehensive Review of Design and Implementation of Hardware Accelerators

Hardware accelerators based on Field-Programmable Gate Arrays (FPGAs) and System-on-Chip (SoC) platforms continue to be adopted for performance- and energy-constrained computing due to their reconfigurability and ability to tailor datapaths to application needs. This work reviews FPGA-based hardware accelerator development with an emphasis on high-level synthesis (HLS)-driven optimization and the associated design-space trade-offs. Specifically, the paper discusses how HLS directives and architectural choices influence throughput, area utilization, and timing, and how these decisions expand the effective design space as resource availability and target clock constraints change. The study further surveys representative design-space exploration (DSE) practices and summarizes practical strategies for power monitoring and power-efficient optimization in FPGA and SoC implementations. The goal is to provide a structured reference that supports researchers and performance engineers in selecting optimization approaches, reasoning about directive-driven design complexity, and improving processing efficiency on reconfigurable platforms.