A complete design of a RISC processor for pedagogical purposes
A complete design of a RISC processor for pedagogical purposes
H. Elaarag
2009 · DOI: 10.5555/1629036.1629069
Journal of Computing Sciences in Colleges (JCSC; Formerly: Journal of Computing in Small Colleges) · 9 Citations
TLDR
In this paper, the design of an instruction set architecture is presented to address the need of providing a simple but realistic hands-on experience to computer organization and architecture students and a recommendation to the chips needed to build this processor is given.