The Via Impedance Simulation and Control in PCB Manufacture for 112Gb/s

As AI (Artificial Intelligence), cloud computing, and 5.5G technologies continue to advance, the demand for bandwidth has surpassed what 400G can provide. In response, the IEEE and OIF Standards Institute have developed and released protocol specifications for 800G and 112Gb/s, prompting service providers and CSPs (Cloud Service Providers) to turn to 800G products for launch and mass production. The design of the 800G employs a single-rate architecture operating at 112Gb/s Serdes, which imposes stringent signal integrity requirements across the entire PCB (Printed Circuit Board) link. To meet the tight impedance and insertion loss tolerances necessary for 112Gb/s design, PCBs incorporate sophisticated designs including the use of ultra-low-loss CCL (Copper Clad Laminate) with hybrid (FR-4) design, very low profile copper foil, low Dk (Dielectric Constant) and low Df (Dispersion Factor) glass fabric, as well as low etch and profile oxide treatments. However, managing transmission line impedance and insertion loss alone is insufficient for meeting the demands of 112Gb/s; via impedance must also be meticulously controlled to ensure impedance continuity throughout the link. The complexity of via structures presents challenges in measuring them using traditional TDR (Time Domain Reflectometer) and VNA (Vector Network Analyzer) equipment. Conventional via impedance simulation software is inadequate for accurate simulation for real PCB via design. To address this issue, the study utilizes three-dimensional electromagnetic simulation software to construct a differential pair model. The PCB Gerber file is imported and the actual via design including the BGA area and press fit is modeled. It investigates the impact of key PCB design elements such as different laminate dielectric constants (Dk), annular ring and anti-pad design, back drill stubs, and drill size selection. The simulation model is adjusted based on measured impedance data from the PCB to refine the impedance prediction model and make simulations that consider the influence of PCB manufacturing deviations on via impedance and insertion loss. Additionally, PCB control tolerance was established. The study demonstrates that after optimization, the via impedance can differ from the transmission line impedance by less than 5%, and the insertion loss can be improved by approximately 2%. This simulation model effectively aids in controlling via impedance, ensuring manageable insertion loss for PCB links, and holds promising applications in high-speed communication scenarios.