System Technology Co-Optimization Through Simulation for UCIe and HBM3 High-Density Bridges on a Unified 2 μm RDL Platform

Advanced packaging solutions such as Universal Chiplet Interconnect Express (UCIe) and High Bandwidth Memory (HBM3) are critical for meeting growing bandwidth and integration demands in AI, HPC, and cloud systems. This work presents a comprehensive analysis of high-density UCIe and HBM3 bridges implemented on a $2 \mu ~\mathrm{m}$ redistribution layer (RDL) platform with four metal layers and Ground-SignalGround (GSG) routing. Using Keysight SiPro and ADS simulations within a System Technology Co-Optimization framework, we evaluate signal integrity across multiple dielectric materials and termination conditions. Results show that dielectric constant (Dk) is the dominant factor affecting eye height and compliance, whereas loss tangent (Df) has minimal impact. UCIe bridge achieves full compliance up to 32 Gbps across all materials, while HBM3 bridge requires low-Dk materials to maintain compliance at 6.4 Gbps, with stricter constraints imposed at higher data rates. These findings provide practical guidance for co-designing interconnect geometry, material selection, and signaling standards in next-generation modular, high-performance packaging solutions.