Signal Integrity Optimization of High-Speed SerDes Signals in Flip-Chip Package Substrates Using a Parametric 3D Modeling Program
Signal Integrity Optimization of High-Speed SerDes Signals in Flip-Chip Package Substrates Using a Parametric 3D Modeling Program
M. Zhuang,Hei-Chi Yang,3 Authors,Yu-po Wang
Abstract
In the past, optimizing the signal integrity (SI) of high-speed SerDes signals in the packaging substrate required drawing the substrate layout first. The drawing files are then imported into the simulation software to create a 3D model and perform 3D EM simulation. Finally, confirm whether the S parameter generated by the simulation meet the specifications. If the specifications are not met, the drawing will be modified and the above steps will be repeated until the S parameter meet the specifications. This article discusses the use of Python syntax to write a 14-variable automated 3D modeling program, and writes a script to automatically import it into simulation software for simulation and generation of S parameters. The use of parametric 3D modeling programs eliminates the need to draw substrate layouts during initial SI evaluations, and model building only takes 1 second, significantly reducing the time spent on the above-mentioned previous methods. In addition, the generated 3D model occupies less than 1% of the hard disk space of previous models, the DRAM usage for model operation is 65% of that of previous models, and the total simulation calculation time is 20% of that of previous models. In the actual case of SerDes with a data rate of 112Gbps PAM4, the differential insertion loss simulation result at 28GHz using the model generated by the program is -2.3dB, while the differential insertion loss at 28GHz using the actual substrate layout is -2.4dB, with a difference of less than 0.5dB. In addition, the differential return loss simulation result at 28GHz using the model generated by the program is -16.4dB, while the differential return loss simulation result at 28 GHz using the actual substrate layout is -15.2dB, with a difference of less than 3dB. The proposed method has demonstrated its effectiveness and good accuracy and can be used to improve the efficiency of SerDes SI analysis.
