Signal Integrity Analysis of 3D Integrated Interconnect Structures Based on Parallel TSVs

With the advancement of 3D integrated circuit (3D IC) technology, vertical interconnection technologies, such as through-silicon vias (TSVs) and bumps, are widely used in 3D heterogeneous integration, but they also introduce signal integrity issues. This paper presents a 3D interconnect structure based on GSG-type parallel TSVs to investigate the impact of structural parameters on signal integrity in redundant design. HFSS simulations are used to analyze the effects of key parameters, such as TSV spacing, TSV diameter, insulation layer thickness, and bump height. The results show that an appropriate TSV spacing and larger TSV diameter help reduce return loss and insertion loss, thereby improving signal quality. This work provides theoretical guidance for 3D interconnect design, particularly in optimizing redundant design for signal integrity.