Research on the Signal Impedance Optimization Method on 2.5D Si-Interposer Design

With advancements in AI, big data, and cloud computing technologies, 2.5D and 3D packaging solutions are increasingly utilized to enhance IC performance. However, the presence of substantial parasitic capacitance leading to low characteristic impedance underscores the importance of optimizing characteristic impedance. This paper introduces a L-compensation method employing T-coil to enhance the impedance optimization of the 2.5D Si-interposer of DDR5 from micro bump to C4 bump. The optimized design markedly enhances the signal characteristic impedance matching and reduces return loss, significantly improving both eye width and eye height. This optimization approach is easy to implement without additional space costs and can be extended to other high-speed interface signals.