Paving the Way for 64 Gbps PCIe 6.0 End to End Physical Link Compliance in Multi-board Digital System

This paper introduces the four-level pulse amplitude modulation (PAM-4) and its implementation in Peripheral Component Interconnect Express (PCIe) 6.0 communication protocol, to facilitate the large volume of high-resolution data traffic in multi board digital electronic system, such as computing server and modular test instrument platform. Besides that, the link loss budget of each system component, i.e., chip package, board and connector is presented. Moreover, this paper also underlines the vital pre-route consideration from signal integrity standpoint for the physical channel realization on printed wiring board (PWB), including the choice of substrate material, communication link design and the end-to-end channel analysis at 64 Gbps speed grade, to be compliant with the specification of characteristic impedance, insertion loss and eye diagram regulated by PCISIG.