PCIe Gen 6.0 SSD Receiver PAM-4 SI Analysis Based on End-Port Time-domain Measurements for Unknown System Channel

This paper presents a system-level PCI Express (PCIe) Gen 6.0 PAM-4 receiver (Rx) signal integrity (SI) analysis using time-domain measurements at a system channel-end test point (TP) without any end-to-end passive channel information such as a S-parameter model. Insertion loss (IL), return loss (RL), and near-end/far-end crosstalk (NEXT/FEXT) for the entire interconnect path at each Nyquist frequency for PCIe Gen 3.0, 4.0, and 5.0 are calculated as a result of measuring voltage waveforms at the TP when the host as the transmitter (Tx) transmits compliance bit pattern. We demonstrated for the first time that reliable Rx PAM-4 SI analysis is possible for entire end-to-end PCIe Gen 6.0 interface channel using a mimic channel model based on the calculated IL, RL, NEXT, and FEXT values.