PCIe Gen-5 Design Challenges of High-Speed Servers

Supporting PCIe Gen-5 in high-speed servers has become a challenge to designers. Parasitic effects that were benign at PCIe Gen-4 speeds are impacting PCIe Gen-5 operations adversely. Optimizing signal and ground via placement, anti-pad dimensions, AC capacitor placement and trace routing in dense pin area are becoming important as sensitivity to loss, impedance and crosstalk is high at 32 Gbps. In this paper, few approaches to minimize channel impedance discontinuity and near-end/far-end crosstalk (NEXT/FEXT) are discussed. Two channels with optimal design practices and regular design practices are compared and contrasted.