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Numerical Study of a Novel Stacked Structure Trench Capacitor in 2.5D Packaging

Yanze Gao,Hanwen Cui,6 Authors,Zhaofu Zhang

2025 · DOI: 10.1109/ICEPT67137.2025.11157068
International Conference on Electronic Packaging Technology · 0 Citations

Abstract

This paper introduces a novel Deep Trench Capacitor (DTC) structure designed to enhance power integrity in integrated circuits. Unlike conventional DTCs with electrodes and dielectrics arranged on trench surfaces, the proposed stacked structure alternates these components at the trench bottom, stacking them until the trench is fully filled. The two trench sidewalls function as the positive and negative electrode plates of the capacitor. Electrical connection between the electrode layer and a single sidewall is achieved through ion implantation technology, which controls the conductive regions of the electrode layer. In this structure, doped silicon serves as the electrode material, while hafnium oxide acts as the dielectric material. The study uses the finite element method (FEM) to simulate and analyze the electrical and mechanical properties of the proposed structure. By significantly simplifying the electrode lead-out structure, the design enables the compact arrangement of trenches, thereby increasing the capacitance density to 1626.4 nF/mm2. At a frequency of 100 MHz, a 4×5 DTC array composed of this structure exhibits an equivalent series resistance (ESR) of 435mΩ and an equivalent series inductance (ESL) of 1.36pH. The breakdown voltage of this structure is 8.7 V. The electrodes and dielectric layer are fabricated using the HDPCVD process. Thermal and mechanical simulations of the deposition process indicate that the maximum principal stress in the electrodes and dielectric layer during deposition is 7.37 × 10⁸ N/m2, which is below the fracture strength of the material. Finally, the SRIM software was employed to simulate the distribution of dopant elements during the ion implantation process, confirming that the doping of the electrode layer does not affect the dielectric layer. The resonant point of the capacitor is near 10 GHz, indicating that the stacked structure capacitor also performs well at high frequencies. Compared with conventional structures, the novel stacked structure offers higher capacitance density and simpler positive and negative electrode lead - out configurations, making it more suitable for application in ultra - high - density packaging.