Modeling and Characterization of thin Al2O3–HfO2 stacked Metal-Insulator-Metal and Deep Trench Decoupling Capacitors for Advanced Packaging Applications

This paper presents a complete modeling and characterization methodology for Metal–Insulator–Metal (MIM) capacitors and Deep Trench Capacitors (DTCs) for advanced 2.5D/3D packaging applications. Geometry-based models are constructed using detailed structural and material parameters, and closed-form RLC expressions are derived and implemented as compact model components. These models are cross-validated against HFSS and Q3D Extractor simulations. For MIM structures, the magnitude error of the compact RLC model relative to HFSS remains below 0.3% for balanced array configurations (2×2 and 5×5). It increases modestly to 2.97% and 5.99% for extreme 1×10 and 10×10 layouts, respectively. For DTC structures, parameter sweeps over dielectric constant εrdk_bot, dielectric thickness tdk_bot, and electrode thickness tm are performed, using HFSS as the golden reference and SPICE AC analysis of the closed-form RLC model for S-parameter comparison. Across the entire DTC dataset, the S21 magnitude error is within about 6%, with the worst case 6% at 10 GHz for the most complex 5×5 array; the maximum capacitance error of 3.38% also occurs at the same 5×5 configuration with minimum dielectric thickness, consistent with the peak S21 deviation, and this 5×5 pattern also shows the strongest frequency-dependent error fluctuation indicating compact model error increased with n×n size. Moreover, for the most complex DTC 5×5 array, the compact-model SPICE simulation achieves a speedup of approximately 5,000× over HFSS while maintaining an acceptable S21 magnitude error.