Low-noise Design for Power Delivery Network in 2.5D Integrated Microsystem

Power delivery network (PDN) plays an important role in high-density integrated microsystem package to supply clean and stable power. High speed synchronous switch, shared silicon substrate and small integrated space always cause large transient changes in current and EMI, which make the design of PDN more difficult. This paper focuses on the core power supply design of the CPU in 2.5D integrated microsystem to realize low noise PDN, whose impedance must be less than 0.1Ω at frequencies below 5GHz. The researched PDN is composed of TSV-interposer PDN and HTCC-substrate PDN. An effective methodology called chip-interposer-substrate co-design and decoupling capacitors (de-cap) co-optimization is presented. For decoupling capacitors, deep trench capacitors (DTC) are used in TSV interposer and surface mount capacitors (SMC) are used on HTCC substrate. First, the decoupling effect of DTCs in TSV interposer and SMCs on HTCC substrate are compared for the whole microsystem PDN in term of frequency domain. Meanwhile, three kinds of capacitance and distributions of DTCs in TSV interposer are also discussed. It carries out that DTCs in TSV interposer can obtain flat impedance in wide frequency band, especially frequencies upper than 100MHz. From 100MHz to 5GHz, the impedance of PDN with multiple small DTCs is maximally reduced by 4Ω than SMCs. Furthermore, the low voltage noise generated by DTCs is verified in term of time domain. Circuit is built using PDN’s S parameter and chip power model (CPM) and transient voltage analysis is done. For universality, CPM models of three CPU chips are discussed. All the three results show that DTCs can significantly improve the PDN performance. PDN with DTCs compared to SMCs, the maximum voltage noise is reduced by 385.6mV.