Determining PCIe5 Jitter Margin using SIPI Co-Sim

This paper explores Signal Integrity Power Integrity relationship in a dual reference package design and understanding of High-Speed Interconnects circuit's behavior through Jitter Transfer Function. Using PCIe5 as a case study, a SIPI co-simulation methodology is proposed where it first decomposed the power noise into frequency spectrums and then injected these noise spectrums to the simulation testbench for dual referencing impact assessment on PCIe5 margin. Simulation results shown that the power supply induced jitter has high influence on the signaling performance at mid frequencies between 4MHz-80MHz, which is well correlated to the jitter transfer function's bandpass filter behavior of PCIe5.