Design of 2.5D Interposer in High Bandwidth Memory and Through Silicon Via for High Speed Signal

The 2.5D interposer becomes a crucial solution to realize

grand bandwidth of HBM for the increasing data requirement of high

performance computing (HPC) and Artificial Intelligence (AI)

applications. To overcome high speed switching bottleneck caused by the large

resistive and capacitive characteristics of interposer, design methods to

achieve an optimized performance in a limited routing area are proposed. Unlike

the conventional single through silicon via (TSV), considering the reliability,

multiple TSV are used as the robust 3D interconnects for each signal path. An

equivalent model to accurately describe the electrical characteristics of the

multiple TSVs, and a configuration pattern strategy of TSV to mitigate

crosstalk are also proposed.