Crosstalk Mitigation for Enabling DDR4 3.2Gbps External Memory Interface in FPGA with Optimized Package-Board Co-Design

Crosstalk mitigation with package-board co-design enhancements is needed for enabling DDR4 3.2Gbps. The proposed optimized 4:1 IO:GND package ball arrangement with alternated deep-shallow board vias can be used as an optimal solution for enabling DDR4 3.2 Gbps without cost adder. This scheme effectively reduces the signals coupling of horizontal and vertical routing structure in package and board design. The results show that we able to gain 50% of channel margin with the proposed solution.