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A 0.00175 mm2 and 9.62 μW per Channel Direct-Digitization Front End With EDO Compensation for Neural Probes With a Spatial Resolution of 35 μm

Roman Willaredt,Christoph Grandauer,2 Authors,Y. Manoli

2025 · DOI: 10.1109/jssc.2025.3555007
IEEE Journal of Solid-State Circuits · 5 Citations

Abstract

This article presents a recording front end tailored to modular CMOS neural probes with high spatial resolution and integrated on-site digitization. The architecture leverages a folded-cascode operational transconductance amplifier (OTA)-C two-step delta-sigma ( ΔΣ\Delta \Sigma ) converter with a four-channel time multiplexing to enable efficient signal processing. It incorporates an automatic common-mode (CM) adjustment system that compensates for electrode dc offsets (EDOs) and drifts across a dynamic range of 97.7 mV. With a supply voltage of 1.2 V, the system consumes 9.62 μ9.62~{\mu } W/channel, including data transfer. Fabricated using a 180-nm SOI process, the front end occupies only 0.00175 mm2 per channel, supporting the seamless integration of 192 recording channels beneath the probe electrodes. The front end achieves an average noise level of 7.59 μ7.59~{\mu } Vrms over the full bandwidth from dc to 10 kHz. Integrated into neural probes with platinum microelectrodes, the system attains an average noise in the AP band (0.3–10 kHz) from 11.22 to 16.29 μ16.29~{\mu } Vrms, depending on the size of the electrodes. The probe design features a two-column electrode pitch of 35 μ35~{\mu } m and requires only five external pads, highlighting its potential for scalable neural recording applications.