3D Electromagnetic Simulation and Modeling for DTCO of Decoupling High-Density Capacitor in Silicon Interposer for HPC Applications

In this paper, we present a Design-Technology Co-Optimization (DTCO) methodology of a heterogeneous 2.5D system that aims at integrating a passive interposer with HPC chiplets. The interposer comprises 3D high-density decoupling capacitors with the power delivery network (PDN) of the HPC chiplets. The proposed methodology is based on the discretization of the interposer into unit-cells and uses spatially distributed SPICE modeling to achieve voltage drop optimization, thus improving the performance of the chiplets at system level, in iterative loop processes. Using Electromagnetic (EM) simulation for unit-cells, incorporating boundary conditions that can be customized, we found out that neighboring cells play a significant role in the voltage drop seen inside the unit-cell as a result of resistive and inductive distributed parasitic interconnects. Consequently, these adjacent cells were incorporated into the EM simulation set-up for accurate power integrity analysis at system level.