112G High Speed Interface Package Design and Simulation

With the increasing speeding of high-speed serdes signal, IEEE and OIF Standards Institute have developed and released detailed protocol specifications, It can be seen from the protocol specification that 112G serdes has much higher fundamental frequency about 28GHz, and higher challenges for the system and package design. For example: differential IL, XTALK, differential RL, common mode noise etc, so the design and simulation of 112G high-speed serdes package are facing more and more serious challenges. In this paper, the electrical performance of common mode noise and crosstalk in the package design of 112G high-speed serdes are compared and analyzed, which will seriously affect communication system performance. Through simulation, optimization and analysis, the impact of the performance index caused by the common mode noise and crosstalk of package power supply in different ball-map layouts is quantitatively analyzed to find the optimal design. Ensure the best package routing performance of the 112G serdes design, and ensure that the performance of the package chip meets the design requirement and tap-out.