A graph placement methodology for fast chip design
A graph placement methodology for fast chip design
Azalia Mirhoseini,Anna Goldie,17 作者,J. Dean
2021 · DOI: 10.1038/s41586-021-03544-w
Nature · 引用数 616
TLDR
A deep reinforcement learning approach to chip floorplanning that automatically generates chip floorplans that are superior or comparable to those produced by humans in all key metrics, including power consumption, performance and chip area.